FIG. 6 shows a specific circuit construction of a band gap reference voltage circuit disclosed in JP-A-2003-157119. A band gap reference voltage circuit 1 comprises a band gap cell circuit 2, a differential pair 3, a current mirror circuit portion 4, a gain forming portion 5 and an emitter follower circuit portion 6.
In the band gap cell circuit 2, a series circuit comprising a resistor R11 and an NPN transistor T11, and a series circuit comprising a resistor R12, an NPN transistor T12 and a resistor R13 are connected to each other in parallel between a reference voltage output line VBG and the ground. The bases of transistors T11 and T12 are commonly connected to the collector of the transistor T11. The resistance values of the resistors R11, R12 and R13 are adjusted so that the transistors T11 and T12 are driven with different current densities (that is, asymmetrical current is supplied to the transistors T11 and T12), whereby the band gap cell circuit 2 acts to compensate for the characteristic variation with respect to the temperature.
The differential pair 3 comprises an NPN transistor T13 having the base to which the collector (connection point A) of the transistor T11 is connected, an NPN transistor T14 having the base to which the collector (connection point B) of the transistor T12 is connected, and a resistor R14 connected between the emitter of each of the transistors T13 and T14 and the ground.
The current mirror circuit portion 4 comprises PNP transistors T15 and T16 whose bases are connected to each other. The emitters of the transistors T15 and T16 are connected to the reference voltage output line VBG through resistors R15 and R16, and the collectors of the transistors T15 and T16 are connected to the collectors of the transistors T13 and T14, respectively. The same level current is supplied to the transistors T15 and T16.
The gain forming portion 5 has a PNP transistor T17 and an NPN transistor T18. The emitter of the transistor T17 is connected to the reference voltage output line VBG through an resistor R17, the collector thereof is connected to the ground through a resistor R18 and the base thereof is connected to the collector of the transistor T14. The transistor T18 is disposed to apply a gain to amplify variation of current supplied to the transistor T14 through the transistor T17. The collector of the transistor T18 is connected to the power source VCC through a resistor R19, the base thereof is connected to the collector of the transistor T17, and the emitter thereof is connected to the ground.
The emitter follower circuit portion 6 comprises the resistor R19 and the NPN transistor T19. the collector of the transistor T19 is connected to the power source VCC, the base thereof is connected to the collector of the transistor T18, and the emitter thereof is connected to the reference voltage output line VBG. The differential pair 3, the current mirror circuit portion 4, the gain forming portion 5 and the emitter follower circuit portion 6 constitute an operational amplifier 7.
Capacitors C1 to C3 are provided for phase compensation to prevent oscillation of the operational amplifier 7. The capacitor C1 is connected between the collector and base of the transistor T14, the capacitor C2 is connected between the collectors of the transistor T14 and T17, and the capacitor C3 is connected between the collectors of the transistors T17 and T18.
Next, the operation of the band gap reference voltage circuit 1. When the collector currents of the transistors T11 and T12 are represented by Ic1 and Ic2, and the base-emitter voltages (junction voltages) of the transistors T11 and T12 are represented by VBE11 and VBE12, the current Ic2 flowing in the resistor R13 is equal to the current value corresponding to the differential voltage of the respective base-emitter voltages VBE11 and VBE12, and represented by the following equation.Ic2=(VBE11−VBE12)/R13
Furthermore, when the base currents of the transistors T11 and T12 are represented by Ib1 and Ib2 respectively and the emitter currents of the transistors T11 and T12 are represented by Ie1 Ie2 respectively, the respective base currents Ib1 and Ib2 are sufficiently small and thus can be neglected as compared with the respective collector currents Ic1 and Ic2, and thus the respective emitter currents Ie1, Ie2 can be regarded as being equal to the collector currents Ic1 and Ic2, respectively. Accordingly, when the base-emitter voltages VBE11 and VBE12 are varied due to characteristic variation of the transistors T11 and T12, the collector current Ic2 flowing in the resistor R13 varies in connection with the variation of the base-emitter voltage VBE11, VBE12, and thus the relationship between the potentials (reference voltage) of the connection points A and B is varied. The potentials of the connection points A and B are applied as the base voltages of the two transistors T13 and T14 constituting the differential pair 3.
Here, when the collector currents of the transistors T13 and T14 are represented by I1 and I2 respectively and the current flowing in the resistor R14 connected to the collectors of the transistors T13 and T14 is represented by I, the currents I1 and I2 are basically equal to I/2 because the collector currents I3 and I4 of the transistors T15 and T16 are equal to each other. For example, when the current I2 flowing in the transistor T14 is about to increase to be larger than I/2, the collector currents I3 and 14 of the transistors T15 and T16 must keep the same value, and thus an insufficient current component is compensated by the base current of the transistor T17. Accordingly, the collector current I5 of the transistor T17, that is, the current flowing in the resistor R18 is increased, and in connection with this current increase, the collector current I6 of the transistor T18 is also increased.
The collector current I6 corresponds to the current I7 flowing in the resistor R19, and thus the base potential and the emitter potential of the transistor T19 is reduced by the increase of the collector currents I6 and I7. By the above action, the potentials at the connection points A and B are adjusted, and the output voltage VBG is fed back so that the potentials are controlled to be fixed. The emitter follower circuit portion 6 is subjected to level shift by only the amount corresponding to the base-emitter voltage to set the output voltage VBG. That is, in the band gap reference voltage circuit 1, the collector potentials of the transistors T11 and T12 in the band gap cell circuit 2 are amplified by the differential pair 3 and the current mirror circuit portion 4, and further amplified by the transistors T17 and T18 in the gain forming portion 5.
The band gap reference voltage circuit 1 thus constructed is designed so that amplification is carried out at plural stages in the operational amplifier 7. Therefore, the total gain of the circuit is increased, and also phase-delay is more liable to occur because the operation of each circuit portion is delayed, so that the circuit may fall into an oscillation operation with an extremely high probability. Therefore, the capacitors C1 to C3 are needed for phase compensation to prevent oscillation. When a semiconductor integrated circuit is constructed, capacitors occupy a very large area, and thus the circuit scale is increased. In addition, the start-up of the circuit operation when power is turned on is further delayed.
In JP-A-2003-157119, it is illustrated that only one capacitor for phase compensation is disposed. However, it is experimentally obvious that if three capacitors C1 to C3 are disposed as shown in FIG. 6, it would be actually difficult to surely suppress the oscillation operation.